174DFN 8L ROHS

174DFN Series MINATURE/NON-MAGNETIC 8-PIN DFN PACKAGE P-CHANNEL JFET SWITCH FEATURES TOP VIEW S 7 6 Replacement For SILICONIX J/SST174 SERIES LOW ON RESISTANCE rDS(on) ≤ 85Ω LOW GATE OPERATING CURRENT ID(off) = 10pA ABSOLUTE MAXIMUM D 8 5 RATINGS1 L17F YYWW @ 25 °C (unless otherwise stated) Maximum Temperatures Storage Temperature -55 to 150°C Junction Operating Temperature -55 to 135°C Maximum Power Dissipation Continuous Power Dissipation3 350mW Maximum Currents Gate Current 1 IG = -50mA 2 Maximum Voltages Gate to Drain Voltage VGDS = 30V Gate to Source Voltage VGSS = 30V 3 G 4 LEADS 1, 2, 4, 5 & 7 – NO CONNECTION COMMON ELECTRICAL CHARACTERISTICS @ 25 °C (unless otherwise stated) SYMBOL CHARACTERISTIC MIN BVGSS Gate to Source Breakdown Voltage VGS(F) Gate to Source Forward Voltage IGSS IG ID(off) TYP MAX UNITS 30 V -0.7 Gate Reverse Current 0.01 Gate Operating Current 0.01 Drain Cutoff Current -0.01 1 CONDITIONS IG = 1µA, VDS = 0V IG = -1mA, VDS = 0V VGS = 20V, VDS = 0V nA -1 VDG = -15V, ID = -1mA VDS = -15V, VGS = 10V SPECIFIC ELECTRICAL CHARACTERISTICS @ 25 °C (unless otherwise stated) SYMBOL VGS(off) IDSS rDS(on) CHARACTERISTIC Gate to Source Cutoff Voltage Drain to Source Saturation Current 174DFN 175DFN 176DFN 177DFN UNITS CONDITIONS MIN MAX MIN MAX MIN MAX MIN MAX 5 10 3 6 1 4 0.8 2.25 V VDS = -15V, ID = -10nA -20 -195 -7 -90 -2 -55 -1.5 -30 mA VDS = -15V, VGS = 0V 300 Ω VGS = 0V, VDS = -0.1V Drain to Source On Resistance Linear Integrated Systems 85 125 • 250 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261 Doc 201183 07/25/2019 Rev#A4 ECN#174DFN Series SWITCHING CIRCUIT SWITCHING CHARACTERISTICS SYMBOL td(on) tr td(off) tf CHARACTERISTIC TYP Turn On Time 10 Turn On Rise Time 15 Turn Off Time 10 Turn Off Fall Time 20 UNITS CONDITIONS ns VGS(L) = 0V VGS(H) = 10V See Switching Circuit 1.2kΩ VGS(H) RL VGS(L) 0.1µF RG SWITCHING CIRCUIT PARAMETERS 7.5kΩ 174-DFN 175-DFN 176-DFN 177-DFN VDD -10V -6V -6V -6V VGG 20V 12V 8V 5V RL 560Ω 750Ω 1800Ω 5600Ω RG 100Ω 220Ω 390Ω 390Ω ID(on) -15mA -7mA -3mA -1mA 51Ω 1.2kΩ Scope 51Ω 51Ω DFN PACKAGE TOP VIEW BOTTOM VIEW SOLDER PAD PITCH & DIMENSIONS EXPOSED PAD 1.80±0.05 (2 SIDES) 1.60±0.15 5 PACKAGE OUTLINE 8 0.20 MIN 2.0±0.10 (4 SIDES) CHAMFERED CORNER FOR PIN 1 INDICATOR 0.25X0.25 0.90±0.15 0.20 MIN. SIDE VIEW 4 0.76±0.05 0.29±0.10 (8x) 1 0.25±0.05 (8x) 0.50 (6x) TYP. 2.50±0.05 1.05±0.10 (2 SIDES) 0.20 MIN 0.42±0.05 (8X) 0.675±0.05 0.50 (4x) TYP. ALL DIMENSIONS IN MILLIMETERS 0.30 (4x) TYP. 0.25±0.05 (8X) NOTES 1. 2. 3. Absolute maximum ratings are limiting values above which serviceability may be impaired. Pulsed test: PW ≤ 300µS Duty Cycle: 3% 3. Derate 2.8mW/°C above 25 °C. Information furnished by Linear Integrated Systems is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems. Linear Integrated Systems develops and produces the highest performance semiconductors of their kind in the industry. Linear Systems, founded in 1987, uses patented and proprietary processes and designs to create its high performance discrete semiconductors. Expertise brought to the company is based on processes and products developed at Amelco, Union Carbide, Intersil and Micro Power Systems by company founder John H. Hall. Linear Integrated Systems • 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261 Doc 201183 07/25/2019 Rev#A4 ECN#174DFN Series